 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 12 - bit, 170 msps/210 msps/250 msps, 1.8 v dual analog - to - digital converter (adc) data sheet ad9613 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of pate nts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 C 2017 analog devices, inc. all rights reserved. technical support www.analog.com f eatures s n r = 6 9 . 6 dbfs at 185 mhz f in and 25 0 msps sfdr = 8 6 dbc at 185 mhz f in and 25 0 msps ?1 49.9 dbfs/hz input noise at 185 mhz, ?1 dbfs a in and 250 msps total p ower con sumption: 7 70 mw at 250 msps 1.8 v supply voltages lvds (ansi - 644 levels) outputs integer 1 - to - 8 input clock d ivider (625 m h z maximum input) sample rates of up to 2 50 msps if sampling frequencies of up to 4 0 0 mhz internal adc voltage reference flexible analog input range 1 .4 v p - p to 2 .0 v p - p (1.75 v p - p n ominal) adc clock duty cycl e stabilizer 95 db channel isolation/crosstalk serial p ort c ontrol energy - saving power - down modes applications communications diversity radio systems multimode digital receivers (3g) td - scdma, wi max , w - cdma, cdma2000, gsm, edge, lte i/q demodulation syst ems smart antenna systems general - purpose software radios ultrasound equipment broadband data applications general description the ad9613 is a dual 12 - bit, analog - to - digital converter (adc) with sampling speeds of up to 250 msps. the ad9613 is designed to support communications applications where low cost, small size, wide bandwidth , and versatility are desired. the dual adc core s feature a multistage, differential pipelined architecture with integrated output e rror correction logic. each adc features wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer (dcs) is provided to compensate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. the adc output data is routed directly to the two external 12 - bit lvds output ports and formatted as either interleaved or channel multiplexed. flexible power - down options a llow significant power savings, when desired. functional block dia gram 12 12 reference seria l port sclk sdio csb clk+ clk? sync 1 t o 8 clock divider ad9613 vin+ a d0 d1 1 dco or pdwn oeb vin? a vin+b vcm vin?b notes 1. the d0 t o d 1 1 pins represent both the channe l a and channe l b l vds output d at a. a vdd agnd dr vdd 09637-001 . . . . . parallel ddr lvds and drivers pipeline 12-bit adc pipeline 12-bit adc figure 1. programming for setup and control is accomplished using a 3 - wire spi - compatible serial interface. the ad9613 is available in a 64 - lead lf csp and is specified over the industrial temperature range of ? 40c to +85c. this product is protected by a u.s. patent. product highlights 1. integrated dual , 12 - bit , 170 msps /210 msps / 2 50 msps adc s . 2. fast overrange and threshold detect . 3. proprietary differential input maintains excellent snr performan ce for input freq uencies of up to 4 0 0 mhz. 4. sync input allows synchronization of multiple devices. 5. 3 - pin , 1.8 v spi port for register programming and register readback. 6. pin compatibility with the ad9643 , allowing a simple migrat ion up to 14 bits, and with the ad6649 and the ad6643 .
ad9613* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad9613 evaluation board ? ad9643 evaluation board documentation application notes ? an-1142: techniques for high speed adc pcb layout ? an-282: fundamentals of sampled data systems ? an-345: grounding for low-and-high-frequency circuits ? an-501: aperture uncertainty and adc system performance ? an-586: lvds outputs for high speed a/d converters ? an-737: how adisimadc models an adc ? an-741: little known characteristics of phase noise ? an-742: frequency domain response of switched- capacitor adcs ? an-756: sampled systems and the effects of clock phase noise and jitter ? an-807: multicarrier wcdma feasibility ? an-808: multicarrier cdma2000 feasibility ? an-827: a resonant approach to interfacing amplifiers to switched-capacitor adcs ? an-835: understanding high speed adc testing and evaluation ? an-851: a wimax double downconversion if sampling receiver design ? an-878: high speed adc spi control software ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? ad9613: 12-bit, 170 msps/210 msps/250 msps, 1.8 v dual analog-to-digital converter (adc) data sheet technical books ? the data conversion handbook, 2005 user guides ? ug-293: evaluating the ad9643/ad9613/ad6649/ad6643 analog-to-digital converters tools and simulations ? visual analog ? ad9613 ibis model reference materials product selection guide ? rf source booklet technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc tutorials ? mt-001: taking the mystery out of the infamous formula, "snr=6.02n + 1.76db", and why you should care ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" ? mt-075: differential drivers for high speed adcs overview design resources ? ad9613 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9613 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified. ad9613 data sheet rev. d | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 adc dc specifications ............................................................... 3 adc ac specifications ............................................................... 4 digital specifications ................................................................... 6 switching specifications .............................................................. 8 timing specificatio ns .................................................................. 9 absolute maximum ratings .......................................................... 11 thermal characteristics ............................................................ 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 16 equivalent circuits ......................................................................... 22 theory of operation ...................................................................... 23 adc architecture ...................................................................... 23 analog input c onsiderations ................................................... 23 voltage reference ....................................................................... 25 clock input considerations ...................................................... 25 power dissipation and standby mode .................................... 27 digital outputs ........................................................................... 27 adc overrange (or) ................................................................ 27 channel/chip synchronization .................................................... 28 serial port interface (spi) .............................................................. 29 configuration using the spi ..................................................... 29 h ardware interface ..................................................................... 29 spi accessible features .............................................................. 30 memory map .................................................................................. 31 reading the memory map register table ............................... 31 memory map register table ..................................................... 32 memory map register description ......................................... 34 applications information .............................................................. 35 design guidelines ...................................................................... 35 outline dimensions ....................................................................... 36 orde ring guide .......................................................................... 36 re vision hi story 2/2017 r ev. c to rev. d c hanges to table 9 .......................................................................... 14 1/ 2013 re v. b to rev. c changes to features .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ........................................................................... 5 change to logic inputs (sdio) paramter, table 3 ....................... 6 chan ges to table 4 ............................................................................ 8 change to reading the memory map register table section ....... 31 changes to table 14 ........................................................................ 33 change to memory map register description section ............. 34 updated outline dimensions ....................................................... 36 9 / 2011 rev. a to rev. b changes to figure 1 .......................................................................... 1 changes to temperature drif t parameters ................................... 3 changes output offset voltage (v os ), ansi mode typ parameter and output offset voltage (v os ), reduced swing mode parameter ................................................................................ 7 changes dco to data skew (t skew ) parameter s .......................... 8 changes to output enable bar and power - down pin type and pin 47 desc ription .................................................................. 13 changes to figure 5 and pin 7 and pin 8 descriptions ............. 14 changes to pin 42 and pin 43 , output enable bar and power - down pin type, and pin 47 descriptions ................................... 15 changes to typical performance characteristics conditions .. 16 changes to fiugre 43 ...................................................................... 22 add ed adc overrange (or) section ......................................... 27 changes to channel/chip synchronization section ................. 28 changes to r eading the memory map register table section and transfer register map section ................................ 31 changes to register 0x02, bits[5:4] .............................................. 32 changes to register 0x16, bit 5 .................................................... 33 add ed register 0x3a ..................................................................... 34 deleted register 0x59 .................................................................... 34 changes to bit 0 mast er sync buffer enable section ............. 34 deleted sync pin con trol (register 0x59) section .................. 34 5/ 2011 re v. 0 to rev. a changes to table 2, ad9613 - 170: worst second or third harmonic and worst other (harmonic or spur) max values and spurious free dynamic range min value ............................. 4 4/ 20 11r e vision 0 : initial version data sheet ad9613 rev. d | page 3 of 36 specifications adc dc specification s a vdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ? 1.0 dbfs differential input, 1.75 v p - p full sca le input range , dcs enabled , unless otherwise noted. table 1 . ad9613 - 170 ad9613 - 210 ad9613 - 250 parameter temp min typ max min typ max min typ max unit resolution full 12 12 12 bits accuracy no missing codes full guaranteed guaranteed guaranteed offset error full 10 10 10 mv gain error full +2/?6 +3/?5 4 %fsr differential nonlinearity (dnl) full 0.5 0.5 0.5 lsb 25c 0.25 0.25 0.25 lsb integral nonlinearity (inl) 1 full 0.5 0.6 0.8 lsb 25c 0.20 0.25 0.28 lsb matching characteristic offset error full 13 13 13 mv gain error full 2.5 +3.5/?2 +3.5/?2.5 %fsr temperature drift offset error full 5 5 5 ppm/c gain error full 7 0 8 0 100 ppm/c input - referred noise vref = 1.75 v 25c 0.39 0.39 0.39 lsb rms analog input input span full 1.75 1.75 1.75 v p -p input capacitance 2 full 2.5 2.5 2.5 pf input resistance 3 full 20 20 20 k? input common - mode voltage full 0.9 0.9 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd 1 full 230 250 241 265 252 275 ma i drvdd 1 full 142 160 159 185 176 210 ma power consumption sine wave input 1 (drvdd = 1.8 v) full 670 738 720 810 770 873 mw standby power 4 full 90 90 90 mw power - down power full 10 10 10 mw 1 measured with a low input frequency, full - scale sine wave. 2 input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured with a dc input and the clk pin i nactive (that is, set to avdd or agnd). ad9613 data sheet rev. d | page 4 of 36 adc ac specification s avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vi n = ? 1.0 dbfs differential input, 1.75 v p - p full scale input range , unless otherwise noted. table 2 . ad9613 - 170 ad9613 - 210 ad9613 - 250 parameter 1 temp min typ max min typ max min typ max unit signal - to - noise - ratio (snr) f in = 30 mhz 25c 70.1 70.1 70.0 dbfs f in = 90 mhz 25c 70.0 70.0 69.8 dbfs full 69.3 69.2 dbfs f in = 140 mhz 25c 69.8 69.8 69.6 dbfs f in = 185 mhz 25c 69.5 69.5 69.2 dbfs full 67.8 dbfs f in = 220 mhz 25c 69.4 69.3 69.0 dbfs signal - to - noise and distortion (sinad) f in = 30 mhz 25c 69.1 69.1 69.0 dbfs f in = 90 mhz 25c 69.0 69.0 68.8 dbfs full 68.2 68 dbfs f in = 140 mhz 25c 68.8 68.8 68.6 dbfs f in = 185 mhz 25c 68.5 68.5 68.2 dbfs full 66.5 dbfs f in = 220 mhz 25c 68.4 68.3 68.0 dbfs effective number of bits (enob) f in = 30 mhz 25c 11.2 11.2 11.2 bits f in = 90 mhz 25c 11.2 11.2 11.1 bits f in = 140 m hz 25c 11.1 11.1 11.1 bits f in = 185 mhz 25c 11.1 11.1 11.0 bits f in = 220 mhz 25c 11.1 11.0 11.0 bits worst second or third harmonic f in = 30 mhz 25c ?94 ?94 ?90 dbc f in = 90 mhz 25c ?92 ?94 ?89 dbc full ?7 8 ?80 dbc f in = 140 mhz 25c ?87 ?88 ?86 dbc f in = 185 mhz 25c ?89 ?83 ?86 dbc full ?80 dbc f in = 220 mhz 25c ?80 ?83 ?85 dbc spurious - free dyna mic range (sfdr) f in = 30 mhz 25c 94 90 92 dbc f in = 90 mhz 25c 92 90 89 dbc full 7 8 80 dbc f in = 140 mhz 25c 87 88 86 dbc f in = 185 mhz 25c 89 83 86 dbc full 80 dbc f in = 220 mhz 25c 83 83 85 dbc worst other (harmonic or spur) f in = 30 mhz 25c ?97 ?95 ?93 dbc f in = 90 mhz 25c ?96 ?95 ?92 dbc full ?7 8 ?80 dbc f in = 140 mhz 25c ?97 ?97 ?91 dbc f in = 185 mhz 25c ?91 ?96 ?91 dbc full ?80 dbc f in = 220 mhz 25c ?93 ?94 ?89 dbc data sheet ad9613 rev. d | page 5 of 36 ad9613 - 170 ad9613 - 210 ad9613 - 250 parameter 1 temp min typ max min typ max min typ max unit two - tone sfdr f in = 184.12 mhz (?7 dbfs), 187.12 mhz (?7 dbfs) 25c 88 88 88 dbc crosstalk 2 full 95 95 95 db full power bandwidth 3 25c 1000 1000 1000 mhz 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 d bfs on one channel and no input on the alternate channel. 3 full power bandwidth is the bandwidth of operation where typical adc performance can be achieved. ad9613 data sheet rev. d | page 6 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ? 1.0 dbfs differential input, 1.75 v p - p full - scale input range , dcs enabled, unless otherwise noted. table 3 . parameter temp min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl intern al common - mode bias full 0.9 v differential input voltage full 0.3 3. 6 v p - p input voltage range full a gnd avdd v input common - mode range full 0.9 1.4 v high level input current full 10 22 a low level input current full ?22 ?10 a input ca pacitance full 4 pf input resistance full 8 10 12 k? sync input logic compliance cmos /lvds internal bias full 0.9 v input voltage range full agnd avdd v high level input voltage full 1.2 avdd v low level input voltage full agnd 0.6 v high level input current full ?5 +5 a low level input current full ?5 +5 a input capacitance full 1 pf input resistance full 12 16 20 k? logic input (csb) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?5 +5 a low level input current full ?80 +45 a input resistance full 26 k? input capacitance full 2 pf logic input (sclk ) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v h igh level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k? input capacitance full 2 pf logic in puts (sdio ) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ?5 +5 a input resistance full 26 k? input capacitance full 5 pf data sheet ad9613 rev. d | page 7 of 36 parameter temp min typ max unit logic inputs ( oeb, pdwn) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 70 a low level input current full ? 5 + 5 a input resistance full 26 k? input capacitance full 5 pf digital outputs lvds data and or outputs differential output voltage (v od ), ansi mode full 250 350 450 mv output offset voltage (v os ), ansi mode full 1.15 1.2 2 1.35 v differential output voltage (v od ), reduced swing mode full 150 200 280 mv output offset v oltage (v os ), reduced swing mode full 1.15 1.2 2 1.35 v 1 pull up. 2 pull down. ad9613 data sheet rev. d | page 8 of 36 switching specificat ions table 4 . ad9613 - 170 ad9613 - 210 ad9613 - 250 parameter temp min typ max m in typ max min typ max unit clock input parameters input cl ock rate full 625 625 625 mhz conversion rate 1 full 40 170 40 210 40 250 msps clk period, divide - by - 1 mode (t clk ) full 5.8 4.8 4 ns clk pulse width high (t ch ) divide -by - 1 mode, dcs enabled full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns divide -by - 1 mode, dcs disabled full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns divide - by - 2 mode through divide - by - 8 mode full 0.8 0.8 0.8 ns aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0. 1 0.1 ps rms data output parameters lvds mode data propagation delay (t pd ) full 6.0 6.0 6.0 ns dco propagation delay (t dco ) full 6.7 6.7 6.7 ns dco to data skew (t skew ) full 0.4 0.7 1.0 0.4 0.7 1.0 0.4 0.7 1.0 ns pipeline delay (latency) full 10 10 10 cycles aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 0.1 ps rms wake - up time ( f rom standby) full 10 10 10 s wake - up time ( f rom power d own) full 250 250 250 s out - of - range recovery time full 3 3 3 cycles 1 conversion rate is the clock rate after the divider. data sheet ad9613 rev. d | page 9 of 36 timing specification s table 5 . parameter test conditions /comments min typ max unit sync timing requirements see figure 3 for tim ing details t ssync sync to the rising edge of clk setup t ime 0. 3 ns t hsync sync to the rising edge of clk hold t ime 0.4 ns spi timing requirements see figure 58 for spi timing diagram t ds set up time between the dat a and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s set up time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk sh ould be in a logic high state 10 ns t lo w minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 58) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 58 ) 10 ns ad9613 data sheet rev. d | page 10 of 36 timing diagrams vin clk+ clk? dco? dco+ d0 (lsb) parallel interleaved channel multipl exed (even/odd) mode channel multipl exed (even/odd) mode d11 (msb) d0/d1 (lsb) ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a n ? 10 ch b n ? 10 ch a n ? 9 ch b n ? 9 ch a n ? 8 ch b n ? 8 ch a n ? 7 ch b n ? 7 ch a n ? 6 ch a0 n ? 10 ch a1 n ? 10 ch a0 n ? 9 ch a1 n ? 9 ch a0 n ? 8 ch a1 n ? 8 ch a0 n ? 7 ch a1 n ? 7 ch a0 n ? 6 ch a10 n ? 10 ch a11 n ? 10 ch a10 n ? 9 ch a11 n ? 9 ch a10 n ? 8 ch a11 n ? 8 ch a10 n ? 7 ch a11 n ? 7 ch a10 n ? 6 ch b0 n ? 10 ch b1 n ? 10 ch b0 n ? 9 ch b1 n ? 9 ch b0 n ? 8 ch b1 n ? 8 ch b0 n ? 7 ch b1 n ? 7 ch b0 n ? 6 ch b10 n ? 10 ch b11 n ? 10 ch b10 n ? 9 ch b11 n ? 9 ch b10 n ? 8 ch b11 n ? 8 ch b10 n ? 7 ch b11 n ? 7 ch b10 n ? 6 channel a d10/d11 (msb) d0/d1 (lsb) channel b d10/d11 (msb) n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 t a t ch t pd t skew t dco t clk 09637-002 . . . . . . . . . channel a and channel b figure 2. interleaved lvds mode data output timing t ssync t hsync sync clk+ 09637-003 figure 3. sync timing inputs data sheet ad9613 rev. d | page 11 of 36 absolute maximum rat ings table 6 . parameter rating e lectrical avdd to agnd ? 0.3 v to +2.0 v drvdd to a gnd ? 0.3 v to +2.0 v vin+a/ vin+ b, vin ? a/ vin ? b to agnd ? 0.3 v to avdd + 0.2 v clk+, clk ? to agnd ? 0.3 v to avdd + 0.2 v sync to agnd ? 0.3 v to avdd + 0.2 v vcm to agnd ? 0.3 v to avdd + 0.2 v csb to agnd ? 0.3 v to drvdd + 0.3 v sclk to a gnd ? 0.3 v to drvdd + 0.3 v sdio to a gnd ? 0.3 v to drvdd + 0.3 v oeb to a gnd ? 0.3 v to drvdd + 0.3 v pdwn to a gnd ? 0.3 v to drvdd + 0.3 v or+/or ? to agnd ? 0.3 v to drvdd + 0.3 v d0 ? / d0 + t hrough d1 1 ? / d1 1 + to a gnd ? 0.3 v to drvdd + 0.3 v d co+ / dco ? to a gnd ? 0.3 v to drvdd + 0.3 v e nvironmental operating temperature range (ambient) ? 40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65c to +125c stresses at or above those listed under abs olute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. opera tion beyond the maximum operating conditions for extended periods may affect product reliability. thermal characterist ics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the printed circuit b oard (pcb) i ncreases the reliability of the solder joints, maximizing the thermal capability of the package. typical ja is specified for a 4 - layer pcb with solid ground plane. as shown in figure 40 , airflow increa ses heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . table 7 . thermal resistance package type airflow veloci ty (m/s ec ) ja 1, 2 jc 1, 3 jb 1, 4 unit 64 - lead lfcsp 9 mm 9 mm (cp - 64 - 4) 0 26.8 1.14 10.4 c/w 1.0 21.6 c/w 2.0 20.2 c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). esd caution ad9613 data sheet rev. d | page 12 of 36 pin configuration s and function descrip tions 09637-004 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d2? d2+ drvdd d3? d3+ d4? d4+ dco? dco+ d5? d5+ drvdd d6? d6+ d7? d7+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+a avdd avdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clk+ clk? sync dnc dnc dnc dnc dnc dnc drvdd dnc dnc d0? (lsb) d0+ (lsb) d1? d1+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio or+ or? d11+ (msb) d11? (msb) d10+ d10? drvdd d9+ d9? d8+ d8? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9613 parallel lvds t o p view (not to scale) pin 1 indic a t or figure 4. pin configuration (top view) for the lfcsp interleaved parallel lvds mode table 8 . pin function descriptions for the lfcsp interleaved parallel lvds mode pin no. mnemonic type description adc power supplies 0 agnd, exposed pad dle ground analog ground. the exposed thermal pad dle on the bottom of the package provides the analog ground for the part. this exposed pad dle must be connected to ground for proper operation. 4 to 9, 11, 12, 55, 56, 58 d nc do n o t connect . do not connect to these pins. 1 0 , 19, 28, 37 drvdd supply digital output driver supply (1.8 v n ominal ) . 49, 50 , 53 , 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal) . adc analog 1 clk+ input adc clock input true. 2 clk? input adc clock input complement. 51 vin+a input differential analog input pin (+) for channel a. 52 vin ? a input differential analog input pin ( ? ) for channel a. 57 vcm output common - mode level bias output for analog inputs. this pin should be deco upled to ground using a 0.1 f capacitor. 61 vin ? b input differential analog input pin ( ? ) for channel b. 62 vin+b input differential analog input pin (+) for channel b. digital input 3 sync input digital synchronization pin. slave mode only. data sheet ad9613 rev. d | page 13 of 36 pin no. mnemonic type description digi tal outputs 14 d0+ (lsb) output channel a/channel b lvds output data 0 true. 13 d0? (lsb) output channel a/channel b lvds output data 0 complement. 16 d1+ output channel a/channel b lvds output data 1 true. 1 5 d1? output channel a/channel b lvds out put data 1 complement. 1 8 d2+ output channel a/channel b lvds output data 2 true. 17 d2? output channel a/channel b lvds output data 2 complement. 21 d3+ output channel a/channel b lvds output data 3 true. 20 d3? output channel a/channel b lvds output data 3 complement. 23 d4+ output channel a/channel b lvds output data 4 true. 22 d4? output channel a/channel b lvds output data 4 complement. 27 d5+ output channel a/channel b lvds output data 5 true. 26 d5? output channel a/channel b lvds output data 5 complement. 30 d6+ output channel a/channel b lvds output data 6 true. 29 d6? output channel a/channel b lvds output data 6 complement. 32 d7+ output channel a/channel b lvds output data 7 true. 31 d7? output channel a/channel b lvds output data 7 c omplement. 34 d8+ output channel a/channel b lvds output data 8 true. 33 d8? output channel a/channel b lvds output data 8 complement. 36 d9+ output channel a/channel b lvds output data 9 true. 35 d9? output channel a/channel b lvds output data 9 compl ement. 39 d10+ output channel a/channel b lvds output data 10 true. 38 d10? output channel a/channel b lvds output data 10 complement. 41 d11+ (msb) output channel a/channel b lvds output data 11 true. 40 d11? (msb) output channel a/channel b lvds outp ut data 11 complement. 43 or+ output channel a/channel b lvds overrange true. 42 or? output channel a/channel b lvds overrange complement. 25 dco+ output channel a/channel b lvds data clock output true. 24 dco? output channel a/channel b lvds data cloc k output complement. spi control 45 sclk input spi serial clock. 44 sdio input/output spi serial data i/o. 46 csb input spi chip select (active low). output enable bar and power - down 47 oeb input/output output enable bar input (active low). 48 pdwn input/output power - down input (active high). operation depends upon spi mode; this input can be configured as power - down or standby. for further description, refer to table 14. ad9613 data sheet rev. d | page 14 of 36 09637-005 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 b d6?/d7? b d6+/d7+ drvdd b d8?/d9? b d8+/d9+ b d10?/d11? (msb) b d10+/d11+ (msb) dco? dco+ dnc dnc drvdd a d0?/d1? (lsb) a d0+/d1+ (lsb) a d2?/d3? a d2+/d3+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd avdd vin+b vin?b avdd avdd dnc vcm dnc dnc avdd avdd vin?a vin+a avdd avdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clk+ clk? sync dnc dnc orb? orb+ dnc dnc drvdd b d0?/d1? (lsb) b d0+/d1+ (lsb) b d2?/d3? b d2+/d3+ b d4?/d5? b d4+/d5+ notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the analog ground for the part. this exposed paddle must be connected to ground for proper operation. pdwn oeb csb sclk sdio ora+ ora? a d10+/d11+ (msb) a d10?/d11? (msb) a d8+/d9+ a d8?/d9? drvdd a d6+/d7+ a d6?/d7? a d4+/d5+ a d4?/d5? 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9613 channel multiplexed (even/odd) lvds t o p view (not to scale) pin 1 indic a t or figure 5. pin con figuration (top view) for the lfcsp channel multiplexed (even/odd) lvds mode table 9 . pin function descriptions for the lfcsp channel multiplexed (even/odd) lvds mode pin no. mnemonic type description adc power supplies 10, 19, 28, 37 drvdd supply digital output driver supply (1.8 v nominal). 49, 50, 53, 54, 59, 60, 63, 64 avdd supply analog power supply (1.8 v nominal). 4 , 5, 8, 9 , 26, 27 , 55, 56, 58 d nc do n o t connect. do not connect to these pins. 0 agnd, exposed pad dl e ground the exposed thermal pad dle on the bottom of the package provides the analog ground for the part. this exposed pad dle must be connected to ground for proper operation. adc analog 51 vin+a input differential analog input pin (+) for channel a. 52 vin ? a input differential analog input pin ( ? ) for channel a. 62 vin+b input differential analog input pin (+) for channel b. 61 vin ? b input differential analog input pin ( ? ) for channel b. 57 vcm output common - mode level bias output for analog inputs. this pin should be decoupled to ground using a 0.1 f capacitor. 1 clk+ input adc clock input true. 2 clk? input adc clock input complement. digital input 3 sync input digital synchronization pin. slave mode only. digital outputs 7 or b + output chan nel b lvds overrange output true. the overrange indication is valid on the rising edge of the dco. 6 or b ? output channel b lvds overrange output complement. the overrange indication is valid on the rising edge of the dco. data sheet ad9613 rev. d | page 15 of 36 pin no. mnemonic type description 11 b d0?/d1? (lsb) output channe l b lvds output data 1/data 0 complement. 12 b d0+/d1+ (lsb) output channel b lvds output data 1/data 0 true. 13 b d2?/d3? output channel b lvds output data 3/data 2 complement. 14 b d2+/d3+ output channel b lvds output data 3/data 2 true. 15 b d4?/d5? output channel b lvds output data 5/data 4 complement. 16 b d4+/d5+ output channel b lvds output data 5/data 4 true. 17 b d6?/d7? output channel b lvds output data 7/data 6 complement. 18 b d6+/d7+ output channel b lvds output data 7/data 6 true. 20 b d8?/d9? output channel b lvds output data 9/data 8 complement. 21 b d8+/d9+ output channel b lvds output data 9/data 8 true. 22 b d10?/d11? output channel b lvds output data 11/data 10 complement. 23 b d10+/d11+ output channel b lvds output data 11/dat a 10 true. 29 a d0?/d1? (lsb) output channel a lvds output data 1/data 0 complement. 30 a d0+/d1+ (lsb) output channel a lvds output data 1/data 0 true. 31 a d2?/d3? output channel a lvds output data 3/data 2 complement. 32 a d2+/d3+ output channel a l vds output data 3/data 2 true. 33 a d4?/d5? output channel a lvds output data 5/data 4 complement. 34 a d4+/d5+ output channel a lvds output data 5/data 4 true. 35 a d6?/d7? output channel a lvds output data 7/data 6 complement. 36 a d6+/d7+ output cha nnel a lvds output data 7/data 6 true. 38 a d8?/d9? output channel a lvds output data 9/data 8 complement. 39 a d8+/d9+ output channel a lvds output data 9/data 8 true. 40 a d10?/d11? output channel a lvds output data 11/data 10 complement. 41 a d10+/d 11+ output channel a lvds output data 11/data 10 true. 43 or a + output channel a lvds overrange output true. the overrange indication is valid on the rising edge of the dco. 42 or a ? output channel a lvds overrange output complement. the overrange indicati on is valid on the rising edge of the dco. 25 dco+ output channel a/channel b lvds data clock output true. 24 dco? output channel a/channel b lvds data clock output complement. spi control 45 sclk input spi serial clock. 44 sdio input/output spi se rial data i/o. 46 csb input spi chip select (active low). output enable bar and power - down 47 oeb input output enable bar input (active low). 48 pdwn input power - down input (active high). operation depends upon spi mode; this input can be configured as power - down or standby. for further description, refer to table 14. ad9613 data sheet rev. d | page 16 of 36 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, sample rate = maximum sample rate per speed grade , dcs enabled, 1 .75 v p - p differen tial inp ut, vin = ? 1.0 dbfs, 32 k sample, t a = 25c , unless otherwise noted. 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) 09637-013 170msps 90.1mhz @ ?1dbfs snr = 69.7db (70.7dbfs) sfdr = 88dbc figure 6. ad9613 - 170 single - tone fft with f in = 90 .1 mhz 0 ?20 third harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) 09637-014 170msps 185.1mhz @ ?1dbfs snr = 68.9db (69.9dbfs) sfdr = 80dbc figure 7. ad9613 - 170 single - tone fft with f in = 185 .1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) 09637-015 170msps 305.1mhz @ ?1dbfs snr = 67db (68dbfs) sfdr = 79dbc figure 8. ad9613 - 170 single - tone fft with f in = 305.1 mhz 120 100 80 60 40 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09637-016 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 9. ad9613 - 170 single - tone snr/sfdr vs . input amplitude (a in ) with f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 330 360 390 300 270 240 210 180 150 120 90 60 frequency (mhz) snr/sfdr (dbc and dbfs) 09637-017 sfdr (dbc) snr (dbfs) figure 10 . ad9613 - 170 single - ton e snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-018 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 11 . ad9613 - 170 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12 , f in2 = 92.12 mhz, f s = 170 msps data sheet ad9613 rev. d | page 17 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-019 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 12 . ad9613 - 170 two - tone sfdr/imd3 v s. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) 09637-020 170msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 87dbc (94dbfs) figure 13 . ad9613 - 170 two - tone fft with f in1 = 89.12, f in2 = 92.12 mhz, f s = 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 frequency (mhz) amplitude (dbfs) 09637-021 170msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 84dbc (91dbfs) figure 14 . ad9613 - 170 two - tone ff t with f in1 = 184.12, f in2 = 187.12 mhz, f s = 170 msps 100 95 90 85 80 75 70 65 130 140 150 160 120 110 100 90 80 70 60 50 40 170 sample rate (msps) snr/sfdr (dbc and dbfs) 09637-022 snr, channe l b sfdr, channe l b snr, channe l a sfdr, channe l a figure 15 . ad9613 - 170 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90 mhz 12,000 14,000 16,000 10,000 8000 6000 4000 2000 0 n + 1 n n ? 1 output code number of hits 09637-023 0.38lsb rms 16,384 total hits figure 16 . ad9613 - 170 grounded input histogram 0 ?20 third harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 frequency (mhz) amplitude (dbfs) 09637-024 210msps 90.1mhz @ ?1dbfs snr = 69.5db (70.5dbfs) sfdr = 88dbc figure 17 . ad9613 - 21 0 single - tone fft with f in = 90 .1 mhz ad9613 data sheet rev. d | page 18 of 36 0 ?20 third harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 frequency (mhz) amplitude (dbfs) 09637-025 210msps 185.1mhz @ ?1dbfs snr = 68.5db (69.5dbfs) sfdr = 88dbc figure 18 . ad9613 - 21 0 single - tone fft with f in = 185 .1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 frequency (mhz) amplitude (dbfs) 09637-026 210msps 305.1mhz @ ?1dbfs snr = 66.5db (67.5dbfs) sfdr = 75dbc figure 19 . ad9613 - 21 0 single - tone fft with f in = 305 .1 mhz 120 100 80 60 40 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09637-027 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 20 . ad9613 - 21 0 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 snr/sfdr (dbc and dbfs) 09637-028 330 360 390 300 270 240 210 180 150 120 90 60 frequency (mhz) sfdr (dbc) snr (dbfs) figure 21 . ad9613 - 21 0 single - tone snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-029 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 22 . ad9613 - 21 0 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12 , f in2 = 92.12 mhz, f s = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-030 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 23 . ad9613 - 21 0 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 210 ms ps data sheet ad9613 rev. d | page 19 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 frequency (mhz) amplitude (dbfs) 09637-031 210msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 90dbc (97dbfs) figure 24 . ad9613 - 21 0 two - tone fft with f in1 = 89.12, f in2 = 92.12 mhz, f s = 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 frequency (mhz) amplitude (dbfs) 09637-032 210msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 88dbc (95dbfs) figure 25 . ad9613 - 21 0 two - tone fft with f in1 = 184.12, f in2 = 187.12 mhz, f s = 210 msps 100 95 90 85 80 75 70 65 140 160 120 100 80 60 40 180 200 sample rate (msps) snr/sfdr (dbc and dbfs) 09637-033 snr, channe l b sfdr, channe l b snr, channe l a sfdr, channe l a figure 26 . ad9613 - 21 0 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90 mhz 12,000 14,000 10,000 8000 6000 4000 2000 0 n + 1 n n ? 1 n ? 2 output code number of hits 09637-034 0.437lsb rms 16,384 total hits figure 27 . ad9613 - 21 0 grounded input histogram 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09637-035 250msps 90.1mhz @ ?1dbfs snr = 68.9db (69.9dbfs) sfdr = 88dbc figure 28 . ad9613 - 25 0 single - tone fft with f in = 90 .1 mhz 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09637-036 250msps 185.1mhz @ ?1dbfs snr = 68.1db (69.1dbfs) sfdr = 85dbc figure 29 . ad9613 - 25 0 single - tone fft with f in = 185 .1 mhz ad9613 data sheet rev. d | page 20 of 36 0 ?20 third harmonic second harmonic ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09637-037 250msps 305.1mhz @ ?1dbfs snr = 66.5db (67.5dbfs) sfdr = 83dbc figure 30 . ad9613 - 25 0 single - tone fft with f in = 305 .1 mhz 120 100 80 60 40 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 input amplitude (dbfs) snr/sfdr (dbc and dbfs) 09637-038 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 31 . ad9613 - 25 0 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 90.1 mhz 100 95 90 85 80 75 70 65 60 240 260 220 200 180 160 140 120 100 80 60 frequency (mhz) snr/sfdr (dbc and dbfs) 09637-039 snr (dbfs) sfdr (dbc) figure 32 . ad9613 - 25 0 single - tone snr/sfdr vs. input frequency (f in ) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-040 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 33 . ad9613 - 25 0 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 89.12, f in2 = 92.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?7.0 ?21.0 ?32.5 ?44.0 ?55.5 ?67.0 ?78.5 ?90.0 input amplitude (dbfs) sfdr/imd3 (dbc and dbfs) 09637-041 sfdr (dbfs) imd3 (dbc) imd3 (dbfs) sfdr (dbc) figure 34 . ad9613 - 25 0 two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184.12, f in2 = 187.12 mhz, f s = 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09637-042 250msps 89.12mhz @ ?7dbfs 92.12mhz @ ?7dbfs sfdr = 86dbc (93dbfs) figure 35 . ad9613 - 25 0 two - tone fft with f in1 = 89.12 , f in2 = 92.12 mhz, f s = 250 msps data sheet ad9613 rev. d | page 21 of 36 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 10 0 20 30 40 50 60 70 80 90 100 110 120 frequency (mhz) amplitude (dbfs) 09637-043 250msps 184.12mhz @ ?7dbfs 187.12mhz @ ?7dbfs sfdr = 86dbc (93dbfs) figure 36 . ad9613 - 25 0 two - tone fft with f in1 = 184.12, f in2 = 187.12 mhz, f s = 250 msps 100 95 90 85 80 75 70 65 220 200 180 160 140 120 100 80 60 40 240 sample rate (msps) snr/sfdr (dbc and dbfs) 09637-044 snr, channe l b sfdr, channe l b snr, channe l a sfdr, channe l a figure 37 . ad9613 - 25 0 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90 .1 mhz 12,000 14,000 16,000 10,000 8000 6000 4000 2000 0 n + 1 n n ? 1 output code number of hits 09637-045 0.39lsb rms 16,384 total hits figure 38 . ad9613 - 25 0 grounded input histogram ad9613 data sheet rev. d | page 22 of 36 equivalent circuits vin avdd 09637-006 f igure 39 . equivalent analog input circuit 0.9v 15k? 15k? clk+ clk? avdd 09637-007 avdd avdd figure 40 . equivalent clock lnput circuit 09637-063 dr vdd da taout+ v? v+ da taout? v+ v? figure 41 . equivalent lvds output circuit sdio 350? 26k? drvdd 09637-009 figure 42 . equivalent sdio circuit sclk or pdwn or oeb 350 ? 26 k? 09637-010 figure 43 . equivalent sclk, pdwn , or oeb input circuit csb 350 ? 26 k? avdd 09637-011 figure 44 . equivalent csb input circuit avdd avdd 16k? 0.9v 0.9v sync 09637-012 figure 45 . equivalent sync input circuit . data sheet ad9613 rev. d | page 23 of 36 theory of operation the ad9613 has two analog input channels, two filter channels, and two digital output channels. the intermediate frequency ( if ) input signal passes through several stages before appearing at the output port(s) as a filt ered, and optionally , decimated digital signal. the dual adc design can be used for diversity reception of signals, where the adcs operate identically on the sam e carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample f requenc ies from dc to 30 0 mhz using appropriate low - pass or band -pass filtering at the adc inputs with little loss in adc performan ce. operation to 40 0 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. synchronizat i on capability is provided to allow synchronized timing between multiple devices. programm ing and control of the ad9613 are acc omplished using a 3- pin , spi - compatible serial interface. adc architecture the ad9613 architecture consists of a dual front - end sample - and - hold circuit, followed by a pipelined, switched - capacitor adc. the quantized outputs from each stage are combined int o a final 12 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor digital - to - analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differ ential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowi ng digital output noise to be separated from the analog core. during power - down, the output buffers go into a high impedance state. analog input conside rations the analog input to the ad9613 is a differential switched - capacitor circuit that has been desig ned for optimum performance while processing a differential input signal. the clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in figure 46 ). when the input is switche d into sample mode, the signal source must be capable of charging the sampl ing capacitors and settling within 1/2 clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driv ing source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low - pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency ( if ) undersampling applications, the shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. refer to the an - 742 application note, f requency domain response of switched - capacitor adcs ; the an - 827 application note, a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article, transformer - coupled front - end for wideband a/d converters , for more information on this subject. c p ar1 c p ar1 c p ar2 c p ar2 s s s s s s c fb c fb c s c s bias bias vin+ 09637-050 h vin? f igure 46 . switched - capacitor input for best dynamic performance, the source impedances driving vin+ and vin? should be matched, and the inputs should be differentially balanced. input common mode the analog inputs of t he ad9613 are not internally dc biased. in ac - coupled applications, the user must provide this bias externally. setting the device s o that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum performance . an on - board common - mode voltage reference is included in the design and is available from t he vcm pin. using the vcm output to set the input common mode is recommended . optimum per form ance is achieved when the common - mode voltage of th e analog input is set by the vcm pin voltage (typically 0.5 avdd). the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. place t his decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor. ad9613 data sheet rev. d | page 24 of 36 differential input configurations optimum performance is achieved while driving the ad9613 in a differential i nput configuration. for base band a pplications, the ad8138, ada4937-2 , ada4938-2 , and ada4930-2 dif ferential drivers provide excellent performance and a flexible interface t o the a dc. the output common-mode voltage of the ada4930-2 is e asily set with the vcm pin of the ad9613 (see figure 47), and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. v in 76.8 ? 120 ? 0.1f 0.1f 200 ? 200 ? 90 ? avdd 33 ? 33 ? 33? 15 ? 15 ? 5pf 15pf 15pf adc vin? vin+ vcm ada4 930-2 09637-051 figure 47. differential input configuration using the ada4938-2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 48. to bias the analog input, the vcm voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f 0.1f r1 r1 c1 adc vin+ vin? vcm c2 r2 r3 r2 c2 09637-052 r3 33 ? figure 48. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz. excessive signal power can also cause core saturation, which leads to distortion. at input frequenc ies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to ach ieve the true snr performance of the ad9613. for applications where snr is a key p arameter, dif ferential doub le balun coupling is the recommended input configuration (see figure 49). in this configuratio n, the input is ac-co upled, and the cml is provided to each input through a 33 resistor. these r esistors compensate for losses in the input baluns t o provide a 50 impedance to the d river. in the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. based on these parameters, the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 10 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note that the values given in table 10 are for each r1, r2, c2, and r3 component shown in figure 48 and figure 49. an alternative t o usin g a transformer-c oupled input at freque ncies in th e second nyquist zone is to us e an a mplifier with va riable gain. the ad8375 or ad8376 digital variable gain amplifier (dvgas) provides good performanc e for driving the ad9613. figure 50 shows an e xample of the ad8376 driving the ad9613 through a band-pass antialiasing filter. table 10. example rc network frequency range (mhz) r1 series () c1 differential (pf) r2 series () c2 shunt (pf) r3 shunt () 0 to 100 33 8.2 0 15 49.9 100 to 300 15 3.9 0 8.2 49.9 adc r1 0.1f 0.1f 2 v p- p vin+ vin? vcm c1 c2 r1 r2 r2 0.1f s 0.1f c2 33 ? 33 ? s p a p 09637-053 r3 r3 0.1f 33 ? figure 49. d ifferential double balun input configuration data sheet ad9613 rev. d | page 25 of 36 ad8376 ad9613 1h 1h 1nf 1nf vpos vcm 15pf 68nh 2.5k ?U 2pf 301 ? 165 ? 165 ? 5.1pf 3.9pf 180nh 1000pf 1000pf notes 1. all inductors are coilcraft 0603cs components with the exception of the 1h choke indu c tors (0603ls). 2. filter values shown for a 20mhz bandwidth filter centered at 140mhz. 180nh 220nh 220nh 09637-054 figure 50. differential input configuration using the ad8376 (filte r values shown for a 20 mhz band width filter centered at 140 mhz) voltage reference a stable and accurate voltage reference is built into the ad9613 . the full-scale input range can be adjusted by varying the reference voltage via spi. the input span of the adc tracks reference voltage changes linearly. clock input considerations for optimum performance, the ad9613 sample clock inputs, clk+ and clk?, should be clo c ked with a differential sig nal. th e signal is typically ac-couple d into the clk+ and clk? pins via a t ransformer or v ia c apacitors. t hese pi ns are biased i nternally (see f igure 51) a nd require no ext e rn al bi as. if t h e inpu ts are floated, the c lk? pi n is p ulle d low to prevent spurious clocking. 0 9637-055 avdd clk+ 4pf 4pf clk? 0.9v figure 51. simplified equivalent clock input circuit clock input options the ad9613 has a very flexible clock input structure. clock input can be a cmos, lv ds, lvpecl, or sine wave signal. r egardless of t he t ype of si gnal being u s ed, cl o ck so urce jitter is of t he most concern, as described in the jitter considerations secti on. figure 52 and figure 53 show two pre ferable methods for c locking the ad9613 (at clock rates of up to 625 mhz). a low j itter clock source is converted from a single-ended signal to a differential signal using an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recommended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad9613 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9613, while preserving t he fast rise a nd fall times of t h e signal, which are critical t o lo w ji tter performance. 390pf 390pf 390pf schottky diodes: hsms2822 clock input 50 ? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1z xfmr 09637-056 figure 52. transformer coupled differential clock (up to 200 mhz) 390pf 25? 25? 390pf 390pf cloc k input clk? clk+ schottky diodes: hsms2822 adc 09637-057 figure 53. ba lun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac-couple a differential pecl signal to the sample clock input pins, as shown in figure 54. the ad9510, ad9511 , ad9512 , ad9513, ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522, ad9523 , ad9524, and adclk905 / adclk907 / adclk925 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? pecl driver 50k ? 50k ? clk? clk+ clock input clock input ad95xx adc 09637-058 figure 54. differential pecl sample clock (up to 625 mhz) ad9613 data sheet rev. d | page 26 of 36 a third option is to ac - couple a differential lvds signal to the sample clock input pins , as shown in fi gure 55 . the ad9510 , ad9511 , ad9512, ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , and ad9524 clock drivers offer excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ clock input clock input ad95xx lvds driver adc 09637-059 f igure 55 . d ifferential lvds sample clock (u p to 625 mhz ) input clock divider the ad9613 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. t he duty cycle stabilizer (dcs) is enabled by default on power - up . the ad9613 clock divider can be synchronized using the external sync input. b it 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a v alid sync causes the clock divider to reset to its initial state. this synchro - nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock ed ges to generate a var iety of internal timing signals and , as a result , may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics . the ad9613 contains a duty - cycle st abilizer ( dcs ) t hat retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad9613 . jitter o n the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. the duty cycle control loop does not func tion for clock rates less than 4 0 mhz nominally. the loop has a time constant associated with it th at must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is rec ommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter ( t j ) can be calcu lated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ) 10 /( lf snr ? 80 75 70 65 60 55 50 1 10 100 1000 input frequency (mhz) snr (dbc) 09637-060 0.05ps 0.2ps 0.5ps 1ps 1.5ps measured f igure 56 . ad9613 - 250 snr vs . input frequency and jitter the clock input should be treated as an analog signal in cas es where aperture jitter may affect the dynamic range of the ad9613 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillator s make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or an other meth od ), it should be retimed by the original clock at the last step. refer to the an - 501 ap plication note, aperture uncertainty and adc system performance , and the an - 756 application note, sample systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs. data sheet ad9613 rev. d | page 27 of 36 power dissipation an d standby mode as shown in figure 57 , the power dissipated by the ad9613 is proportional to its sample rate. the data in figure 57 w as taken using the same operating conditions as those used for the typical performance characteristics section . 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.5 0.4 0.3 0.2 0.1 0 0 40 60 80 100 120 140 160 180 200 220 240 encode frequency (msps) total power (w) supply current (a) 09637-061 t o t a l power i a vdd i d r vdd figure 57 . ad9613 - 250 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the ad9613 is placed in power - d own mode . in this state, the adc typically dissipates 10 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9613 t o its norma l operati ng mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage . low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when returning to nor mal operation. as a result, wake - up time is related to the time spent in power - down mode , and shorter power - down cycles result in pr oportion ally short er wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see th e memory map register description section and the an - 877 application note , interfacing to high speed adcs via spi , for additional details. digital outputs the ad9613 output drivers can be configured for either ansi lvds or reduced drive lvds using a 1.8 v drvdd supply. as detailed in application note an - 877, interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. digital output enable function (oeb) the ad9613 h as a flexible three - state ability for the digital output pins. the three - state mode is enabled using the oeb pin or through the spi interface. if the o eb pin is low, t he output data drivers are enabled. if the oeb pin is high, the output data drivers are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (d rvdd) and should not exceed that supply voltage. when using the spi interface , the data outputs of each channel can be independently three - stated by usin g the output enable b ar bit (bit 4) in r egister 0x14. because the output data is interleaved, if only one of the two channels is disabled , the output data of the remaining channel is repeated in both the rising and falling output clock cycles. timing the ad9613 provides latched data with a pipeline de lay of 10 input sample clock cycles . data outputs are a vailable one propagation delay (t pd ) after the rising edge of the clock signal. minimize t he length of the output data lines and loads placed on them to reduce transients within the ad9613 . t hese transients can degrade converter dynamic performance. the lowest typical conversion rate of the ad9613 is 40 msps. at clock rates below 4 0 msps, dynamic performance can degrade. data clock output (dco) the ad9613 a lso provides data clock output (dco) intended for capturing the data in an external regis ter. figure 2 show s a timing d iagram of the ad9613 output modes. adc overrange (or) the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange condition is determined at the output of the adc pipeline and, therefore, is subject to a latency of 10 adc clock. an overrange at the input is indicated by this bit 10 clock cycles after it. table 11 . output data format input (v) vin+ ? vin ? , input span = 1.75 v p - p (v) offset binary output mode twos complement mode ( d efault) or vin+ ? vin C less than C 0.875 0000 0000 0000 1000 0000 0000 1 vin+ ? vin C C 0.875 0000 0000 0000 1000 0000 0000 0 vin+ ? vin C 0 1000 0000 0000 000 0 0000 0000 0 vin+ ? vin C + 0.875 1111 1111 1111 0111 1111 1111 0 vin+ ? vin C greater than +0.875 1111 1111 1111 0111 1111 1111 1 ad9613 data sheet rev. d | page 28 of 36 channel/chip synchro nization the ad9613 has a sync input that allows the user flexible synchronization options fo r sync hroniz ing the internal blocks. the sync feature is useful for guarantee ing synchronized o peration across multiple adcs. the input clock divider can be synchronized using the sync input. the divider can be enabled to sync hronize on a single occurre nce of the sync signal or on every occurrence by setting the appropriate bits in r egister 0x 3a . the sync input is internally s ynchronized to the sample clock. h owever , to ensure that there is no timing uncertainty between multiple parts , t he sync input s ignal should be synchroni zed to the input clock signal. the sync input should be driven using a single - ended cmos type signal. data sheet ad9613 rev. d | page 29 of 36 serial port interfac e (spi) the ad9613 spi allows the user to configure the converter for specific functions or operations thr ough a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organi zed into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information, see the an - 877 application note, in terfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin , the sdio pin , and the csb pin (s ee table 12 ). the sclk (serial clock) pin is used to synchronize the read and w rite d ata presented from/to the adc. the sdio (seri al data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active - low control that enables or disab les the read and write cycles. table 12. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a du al - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active - low control that gates the read and write cycles. the falling edge of c sb, in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 58 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a hig h impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase and its length is determined by the w0 and w1 bit s. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruc tion phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback caus es the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb - first mode or in lsb - first mode. msb first is the default on power - up and can be changed via th e spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 12 comp ri se the physical interface between the user programming device and the serial port of the ad9613 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note, microcontroller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9613 to prevent these signals from transitioning at the converter inputs during critical sampling periods. ad9613 data sheet rev. d | page 30 of 36 spi accessible featu res table 13 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application note , interfacing to high speed adcs via s pi . the ad9613 part - specific features are described in the mem ory map register description section . table 13 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs via the sp i offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage digital processing allows the user to enable the synchronization features don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 09637-062 figure 58 . serial port interface timing diagram data sheet ad9613 rev. d | page 31 of 36 m emory ma p reading the memory m ap register table each row in the memory map register table has eight bit locations . the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); and the adc functions registers, including setup, control, and te st (address 0x08 to address 0x 3a ). the memory map register table (see table 14 ) documents the de fault hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x1 4 , the output mode register, has a h exadecimal default value of 0x05. this mean s that bit 0 = 1 and bit 2 = 1 , and the remaining bits are 0s. this setting is the default output format value , which is two s compl e ment . for more information on this function and others, see the an - 877 applic ation note , interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x 2 0 . the remaining register , re gister 0 x3a , is documented in th e memory map register description section. open and reserved locations all address and bit locations that are not included in table 14 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default val ues after the ad9613 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table (see table 14) . logic levels an explanation of logic level terminol ogy follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x 20 and addres s 0x3a are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the trans fer bit is set. the internal update takes place when the transfer bit is set and the bit autoclears. channel specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 14 as local. these local registers and bits can be accessed by setting the appr opriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set durin g an spi read cycle, the part returns the value for channel a . registers and bits designated as global in table 14 affect the entire part and the channel features for which independent settings are not allowed betw een channels. the settings in register 0x05 do not affect the global registers and bits. ad9613 data sheet rev. d | page 32 of 36 memory map register table all address and bit locations that are not included in table 14 are not currently supported for this device. tabl e 14. memory map register s addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration (global) 1 0 l sb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so that lsb - first mode or msb - first mode registers correctly, regardless of shift mode 0x01 chip id (global) 8 - bit chip id[7:0] ( ad9613 = 0x 83) (default) 0x 83 read only 0x02 chi p grade (global) open open speed grade id 0 0 = 25 0 msps 01 = 210 msps 11 = 170 msps open open open open speed grade id used to differentiate devices; read only channel index and transfer registers 0x05 channel index (global) open open open open open ope n adc b (default) adc a (default) 0x03 bits are set to determine which device on the chip receives the next write command; applies to local registers only 0xff transfer (global) open open open open open open open transfer 0x00 synchron - ously transfers dat a from the master shift register to the slave adc functions 0x08 power modes (local) open open external power - down pin function (local) 0 = p ower - down 1 = st a ndby open open open internal power - down mode (local) 00 = normal operation 01 = full power - down 10 = standby 11 = reserved 0x00 determines various generic modes of chip operation 0x09 global clock (global) open open open open open open open duty cycle stabilizer (default) 0x01 0x0b clock divide (global) open open input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 auto - matically cause the duty cycle stabilizer to become active data sheet ad9613 rev. d | page 33 of 3 6 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0d test mode (local) user test mode con trol 0 = continuou s/repeat pattern 1 = single pattern , then 0 s open reset pn long gen reset pn short gen output test mode 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn long seque nce 0110 = pn short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = u nused 1111 = ramp output 0x00 when this register is set, the test data is placed on the output pins in place of normal data 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to ?32 (twos complement format) 0x00 0x14 output mode open open open output enable bar (local) open output invert (local) 1 = normal (default) 0 = inverted output format 00 = offset binary 01 = twos complement (default) 1 0 = gray code 11 = reserved (local) 0x0 5 configures the outputs and the format of the data 0x15 output adjust (global) open open open open lvds o utput drive current adjust 0000 = 3.72 ma output drive current 0001 = 3.5 ma output drive current (default) 00 10 = 3.30 ma output drive current 0011 = 2.96 ma output drive current 0100 = 2.82 ma output drive current 0101 = 2.57 ma output drive current 0110 = 2.27 ma output drive current 0111 = 2.0 ma output drive current (reduced range) 1000 C 1111 = r eserved 0x01 0x16 clock phase control (global) invert dco clock open odd/even mode output enable 0 = disabled 1 = enabled open open open open open 0x00 0x17 dco output delay (global) enable dco clock delay open open dco clock delay [ delay = (31 00 ps register val ue/3 1 +100 ) ] 00000 = 100 ps 00001 = 2 00 ps 00010 = 3 00 ps 11110 = 3 1 00 ps 11111 = 32 00 ps 0x00 0x18 input s pan select (global) open open open full - scale input voltage selection 01111 = 2.087 v p - p 00001 = 1.772 v p - p 00000 = 1.75 v p - p (default) 1111 1 = 1.727 v p - p 10000 = 1.383 v p - p 0x00 full - scale input adjustment in 0.022 v steps 0x19 user test pattern 1 lsb (global) user test pattern 1[7:0] 0x00 0x1a user test pattern 1 msb (global) user test pattern 1[15:8] 0x00 0x1b user test pattern 2 l sb (global) user test pattern 2[7:0] 0x00 0x1c user test pattern 2 msb (global) user test pattern 2[15:8] 0x00 0x1d user test pattern 3 lsb (global) user test pattern 3[7:0] 0x00 ad9613 data sheet rev. d | page 34 of 36 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x1e user test pattern 3 msb (global) user test pattern 3[15:8] 0x00 0x1f user test pattern 4 lsb (global) user test pattern 4[7:0] 0x00 0x3a sync control (global) open open open open open clock divider next sync only clock divider sync enable master sync buffer enable 0x00 1 the channel index register at address 0x05 should be set to 0x03 (default) when writing to address 0x00. memory map register description for more info rmat ion on functions controlled in register 0x00 to register 0x 2 0 , see the an - 877 application note , interfacing to high speed adcs via spi . sync control (register 0x3a) bits[7:3] reserved bit 2 clock divider next sync only if the master sync buffer enable bit (address 0x3a, bit 0) and the clock divider sync enable bit (address 0x3a, bit 1) are high, bit 2 allows the clock divider to sync to the first sync pulse that it receives and to ignore the rest. the cloc k divider sync enable bit (address 0x3a, bit 1) resets after it syncs. bit 1 clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is enabled when bit 1 is high and bit 0 is high. this is continuous sync mode. bit 0 mas ter sync buffer enable bit 0 must be set high to enable any of the sync functions. if the sync capability is not used , this bit should remain low to conserve power. data sheet ad9613 rev. d | page 35 of 36 applications information design guidelines before starting system - level de sign and layo ut of the ad9613 , it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad9613 , it is recommended that two separate 1.8 v supplies be used: one supply should be used for analog (avdd) , and a separate supply should be used for the digital outputs (drvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. these capacitors should be located close to the point of entry at the pc board level and close to the pins of the part with minimal trace length. a single pcb ground plane should be sufficient when using the ad9613 . with proper de coupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to ana log ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the ad9613 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possi ble resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the p ackaging and pcb layout of chip - scale packages, refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (l fcsp) . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 48. for optimal channel - to - channel isolation, a 33 ? resistor should be included between the ad9613 vcm pin and the channel a analog input network connection, as well as between the ad9613 vcm pin and the channel b analog input network connection. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9613 to keep these signals from transitioning at the converter input pin s during critical sampling periods. ad9613 data sheet rev. d | page 36 of 36 outline dimensions compliant to jedec standards mo-220-vmmd-4 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max sea ting plane pin 1 indic at or 6.35 6.20 sq 6.05 pin 1 indic at or 0.30 0.25 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pa d bot t om view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 06-12-2012-c f igure 59 . 6 4- lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 -4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9613 bcpz -170 ?4 0c to +85c 64- lead lead frame chip s cale package [lfcsp_vq ] , 170 msps cp -64 -4 ad9613bcpz -210 ?4 0c to +85c 64- lead lead frame chip scale package [lfcsp_vq], 210 msps cp -64 -4 ad9613bcpz -250 ?4 0c to +85c 64- lead lead frame chip scale package [lfcsp_vq], 250 msps cp -64 -4 ad9613 bcpzrl7 -170 ?4 0c to +85c 64- lead lead frame chip scale package [lfcsp_vq] , 170 msps cp -64 -4 ad9613bcpzrl7 - 210 ?4 0c to +85c 64- lead lead frame chip scale package [lfcsp_vq], 210 msps cp -64 -4 ad9613bcpzrl7 - 250 ?4 0c to +85c 64- lead lead frame chip scale pac kage [lfcsp_vq], 250 msps cp -64 -4 ad9613 - 170ebz e valuation board with ad9613, 170 msps ad9613 - 210ebz e valuation board with ad9613, 210 msps ad9613 -2 50ebz e valuation board with ad9613 , 250 msps 1 z = rohs compliant part. ? 2011C201 7 ana log d evices, i nc. a ll ri ghts res erved. t rademarks an d registered trademarks are the property of their respective owners. d09637-0-2/17(d) |
Price & Availability of AD9613BCPZ-250
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |